clash-lib
Version 1.2.1 revision 0 uploaded by QBayLogic.
Package meta
- Synopsis
- CAES Language for Synchronous Hardware - As a Library
- Description
Clash is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.
Features of Clash:
Strongly typed, but with a very high degree of type inference, enabling both safe and fast prototyping using concise descriptions.
Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.
Higher-order functions, with type inference, result in designs that are fully parametric by default.
Synchronous sequential circuit design based on streams of values, called
Signals, lead to natural descriptions of feedback loops.Support for multiple clock domains, with type safe clock domain crossing.
This package provides:
The CoreHW internal language: SystemF + Letrec + Case-decomposition
The normalisation process that brings CoreHW in a normal form that can be converted to a netlist
Blackbox/Primitive Handling
Front-ends (for: parsing, typecheck, etc.) are provided by separate packages:
Prelude library: https://hackage.haskell.org/package/clash-prelude
- Author
- The Clash Authors
- Bug reports
- https://github.com/clash-lang/clash-compiler/issues
- Category
- Hardware
- Copyright
- Copyright © 2012-2016, University of Twente, 2016-2019, Myrtle Software Ltd, 2017-2019, QBayLogic B.V., Google Inc.
- Homepage
- https://clash-lang.org/
- Maintainer
- QBayLogic B.V. <devops@qbaylogic.com>
- Package URL
- n/a
- Stability
- n/a