clash-prelude
Version 1.2.2 revision 0 uploaded by QBayLogic.
Package meta
- Synopsis
- CAES Language for Synchronous Hardware - Prelude library
- Description
Clash is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.
Features of Clash:
Strongly typed, but with a very high degree of type inference, enabling both safe and fast prototyping using concise descriptions.
Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.
Higher-order functions, with type inference, result in designs that are fully parametric by default.
Synchronous sequential circuit design based on streams of values, called
Signals, lead to natural descriptions of feedback loops.Support for multiple clock domains, with type safe clock domain crossing.
This package provides:
Prelude library containing datatypes and functions for circuit design
To use the library:
Import Clash.Prelude
Alternatively, if you want to explicitly route clock and reset ports, for more straightforward multi-clock designs, you can import the Clash.Explicit.Prelude module. Note that you should not import Clash.Prelude and Clash.Explicit.Prelude at the same time as they have overlapping definitions.
A preliminary version of a tutorial can be found in Clash.Tutorial, for a general overview of the library you should however check out Clash.Prelude. Some circuit examples can be found in Clash.Examples.
- Author
- The Clash Authors
- Bug reports
- https://github.com/clash-lang/clash-compiler/issues
- Category
- Hardware
- Copyright
- Copyright © 2013-2016, University of Twente, 2016-2017, Myrtle Software Ltd, 2017-2019, QBayLogic B.V., Google Inc.
- Homepage
- https://clash-lang.org/
- Maintainer
- QBayLogic B.V. <devops@qbaylogic.com>
- Package URL
- n/a
- Stability
- n/a