clash-verilog
Version 0.7.2 revision 0 uploaded by ChristiaanBaaij.
Package meta
- Synopsis
- CAES Language for Synchronous Hardware - Verilog backend
- Description
CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.
Features of CλaSH:
Strongly typed, but with a very high degree of type inference, enabling both safe and fast prototyping using concise descriptions.
Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.
Higher-order functions, with type inference, result in designs that are fully parametric by default.
Synchronous sequential circuit design based on streams of values, called
Signals, lead to natural descriptions of feedback loops.Support for multiple clock domains, with type safe clock domain crossing.
This package provides:
Verilog Backend
- Author
- Christiaan Baaij
- Bug reports
- http://github.com/clash-lang/clash-compiler/issues
- Category
- Hardware
- Copyright
- Copyright © 2015-2016 University of Twente, 2017, QBayLogic
- Homepage
- http://www.clash-lang.org/
- Maintainer
- Christiaan Baaij <christiaan.baaij@gmail.com>
- Package URL
- n/a
- Stability
- n/a