hsverilog
Version 0.1.0 revision 0 uploaded by junjihashimoto.
Package meta
- Synopsis
- Synthesizable Verilog DSL supporting for multiple clock and reset
- Description
Synthesizable Verilog DSL supporting for multiple clock and reset
- Author
- Junji Hashimoto
- Bug reports
- https://github.com/junjihashimoto/hsverilog/issues
- Category
- Hardware
- Copyright
- n/a
- Homepage
- n/a
- Maintainer
- junji.hashimoto@gmail.com
- Package URL
- n/a
- Stability
- Experimental