netlist
Version 0.3.1 revision 0 uploaded by AndyGill.
Package meta
- Synopsis
- Netlist AST
- Description
A very simplified and generic netlist designed to be compatible with Hardware Description Languages (HDLs) like Verilog and VHDL. Includes a simple inliner.
- Author
- Philip Weaver <philip.weaver@gmail.com>
- Bug reports
- n/a
- Category
- Language
- Copyright
- Copyright (c) 2010 Signali Corp. Copyright (c) 2010 Philip Weaver.
- Homepage
- n/a
- Maintainer
- andygill@ku.edu
- Package URL
- git://github.com/pheaver/netlist-verilog.git
- Stability
- n/a